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IP Design Verification Engineer
4 weeks ago
IP Design Verification Engineer page is loaded IP Design Verification Engineer Apply locations Malaysia, Penang Malaysia, Kulim time type Full time posted on Posted Yesterday job requisition id JR0260001 Job Details: Job Description:
Come join our Chipsets Ingredients Team (CIT) which is part of the Chipsets Silicon Group (CSG).We are looking for a highly motivated logic/RTL pre-silicon verification engineer who will be responsible for the definition and implementation of clocking solution for client and server chipsets in cutting edge internal and external technology nodes. In this unique role the scope of learning opportunity, contributions and influence expands over on-die, multi-die and system level clocking solutions. As system level clocking protocols are the backbone of modern multi-die power management schemes, the role naturally expands into great exposure and contribution opportunities into low-power design architecture.
Your responsibilities will include, but not be limited to one or more of the following aspects of the RTL verification flow which encompasses all aspects of logic design/verification methodology.
Performs functional verification of IP logic to ensure design will meet specification requirements.
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.
Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
Behavioral traits we are looking for:
Strong technical leadership with good communication, interpersonal and problem-solving skills
Motivated, self-directed and able to work effectively both independently and as a team
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Similar Jobs (5) IP Design Verification Engineer locations Malaysia, Penang time type Full time posted on Posted 7 Days Ago Senior IP Design Verification Engineer locations Malaysia, Penang time type Full time posted on Posted 7 Days Ago Senior IP Design Verification Engineer locations Malaysia, Penang time type Full time posted on Posted 14 Days AgoIntel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please click here .
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