RTL Design Engineer

2 weeks ago


Penang, Malaysia UST Malaysia Full time

Direct message the job poster from UST Malaysia

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Who we are:

At UST, we help the world's best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at www.UST.com

Experience: 3+ years

Education: Bachelors or Masters degree in computer engineering/Electrical Engineering

As an RTL Design Engineer, you will be responsible for the complete RTL design workflow, from specifications and architecture to the implementation of various IP designs using Verilog. You will work closely with cross-functional teams, including verification, physical design, and system engineering, to ensure a successful integration of IP components into larger systems.

Key Responsibilities:

  • Develop RTL designs in Verilog for various IP cores, ensuring adherence to high design standards and best practices.
  • Collaborate with system architects to understand specifications and requirements for new IP development.
  • Perform functional simulations and static timing analysis to validate designs.
  • Identify and mitigate potential design issues or bottlenecks early in the design process.
  • Support the verification team in developing test plans and test cases specific to the IP being designed.
  • Participate in design reviews, providing constructive feedback and input to improve design quality.
  • Maintain documentation related to design specifications, implementation details, and design flows.
  • Contribute to the continuous improvement of design processes and methodologies.

Qualifications:

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • A minimum of 3 years of experience in RTL design with a strong proficiency in Verilog.
  • Proven experience in the design and implementation of complex digital circuits.
  • Familiarity with industry-standard design tools and methodologies (e.g., simulation and synthesis tools).
  • Strong understanding of digital design principles, including finite state machines, timing analysis, and low-power design techniques.
  • Experience with FPGA or ASIC design flows is a plus.
  • Excellent problem-solving skills and attention to detail.
  • Strong communication and teamwork skills, with the ability to work collaboratively in a fast-paced environment.

Preferred Qualifications:

  • Experience with other HDL languages such as VHDL is a plus.
  • Familiarity with verification methodologies (e.g., UVM, SystemVerilog) is advantageous.
  • Exposure to RTL design for high-speed interfaces (e.g., PCIe, Ethernet).

Contact Ms. Anna - WhatsApp: +84 935059669

Email: anh.thivannguyen@ust.com

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering Services and Semiconductor Manufacturing

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