Senior IC/SoC Physical Design Engineer | End-to-End Tapeout
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UST Malaysia seeks a Senior Physical Design Engineer with 8+ years of ASIC/SoC experience to lead full-chip and block-level physical design, including floorplanning, CTS, routing and timing closure for advanced nodes.
You will collaborate with RTL, DFT, STA and Verification teams to achieve design closure while optimizing area, power, and performance. You will also support tapeout and silicon bring-up, mentoring junior engineers along the way.