Analog Layout Engineer

2 weeks ago


Penang, Malaysia UST Malaysia Full time

Job Responsibilities:

  • Work closely with circuit designers to complete the physical layout and verification of high-performance analog/mixed-signal CMOS Integrated Circuits using Cadence Virtuoso XL Layout and PVS Verification tools in FinFET technologies.
  • Use problem-solving skills, experience, and creativity to layout circuits that meet size, schedule, and performance specifications while meeting FinFET technology rules.
  • Run physical design verification tools to debug, improve, and verify layout blocks.
  • Collaborate with fellow team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies.

Qualifications:

  • 5+ years' experience in IC layout design in FinFET technology node.
  • Strong understanding of layout fundamentals and best practices.
  • Must be knowledgeable with CAD tools like Cadence Virtuoso XL, PVS/Calibre.
  • Experience with synthesis/advanced place & route tools (Innovus) is a plus.
  • Must be familiar with Cadence Design Environment (CDE) and Unix OS.
  • Programming knowledge in SKILL is a plus.
  • Must have strong communication skills and be a team player.
Seniority Level

Mid-Senior Level

Employment Type

Full-time

Job Function

Engineering Services and Semiconductor Manufacturing

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