Design Verification Engineer

1 week ago


Penang, Malaysia UST Full time
Talent Acquisition @ UST | Talent Sourcing, Recruitment Strategies

Job Responsibilities

  • Develop and execute a comprehensive set of subsystem-level test scenarios covering various use cases (such as Parity/RAS handling and repeater flow) to ensure subsystem-level behaviours/functionality correctness and catch subsystem-level issues.
  • Perform power-aware simulations and ensure low-power design compliance using UPF (Unified Power Format) standards.
  • Develop and maintain reusable verification environments, including testbenches and test cases, using industry-standard methodologies (e.g., UVM).
  • Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the design microarchitecture.
  • Define and implement functional coverage.
  • Perform coverage analysis and identify testing gaps.

Job Requirements

  • Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.
  • 3+ years' professional experience in design verification.
  • Experienced in one or many of these technologies/features - Interconnects, RAS, parity, repeater flow, network on chip, data fabric/router.
  • Strong understanding of verification methodologies, including UVM or equivalent.
  • Proficiency in hardware description and verification languages, such as SystemVerilog.
  • Experience with UPF (Unified Power Format) for low-power design verification.
  • Experience with power-aware simulation methodologies.
  • Experience with scripting languages (Python, Perl, etc.) for automation.
  • Knowledge of assertion-based languages such as SystemVerilog Assertions.
  • Excellent problem-solving, debugging, and analytical skills.
  • Strong communication and collaboration skills, with the ability to work effectively in cross-functional teams.
Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Semiconductor Manufacturing

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