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Static Timing Analysis

1 month ago


Bayan Lepas, Penang, Malaysia Infinecs Systems Full time

The STA engineer is responsible for overseeing all the tasks related to timing constraints and timing closure at block-level and chip-level. You will play a key role in understanding the design goals to meet performance/timing requirements, understand the clocking architecture and their relationship and participate in all timing related discussions.

Responsibilities include (but not limited to):

  • Understand timing syntax, define timing constraints and signoff requirements.
  • Understand how clock architecture relates to timing and performance of design.
  • Timing closure or CPU's GPU's, full chip or large subsystems.
  • Experience with Synopsys SDC, Primetime and STARRC.
  • Scripting with TCL, PERL or Python.

Minimum Qualifications:

  • Bachelor's or Master's degree in electrical/electronics engineering.
  • Minimum 3 years experience analyzing timing in PrimeTime and writing SDC.
  • Previous experience in Clock-Tree-Synthesis optimization and clock KPI analysis.
  • Previous experience in RTL2GDSII implementation and would like to advance into Static Timing Analysis skillset.
  • Prior experience with timing analyzer: Synopsys PrimeTime, Cadence Tempus, Xilinx Vivado, Intel/Altera Quartus.
  • Preferably local candidates.
Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering and Information Technology

Industries

Semiconductor Manufacturing

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