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Senior Verification Specialist

3 weeks ago

Penang, Malaysia UST Full time

About the Job

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We are looking for an experienced Senior Verification Specialist to join our team in UST. The successful candidate will be responsible for developing and implementing advanced verification methodologies using UVM, SystemVerilog, Verilog, and SVA languages.

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Key Responsibilities

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  • ">
  • Design and develop high-quality verification environments and tools.">
  • Collaborate with cross-functional teams to ensure the quality and reliability of our semiconductor products.">
  • Contribute to the growth of our verification team by mentoring junior engineers.">
  • Stay up-to-date with industry trends and emerging technologies.">
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Requirements

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A Master's or Bachelor's degree in Electrical Engineering or Computer Science is required, along with at least 3 years of experience in verification engineering. Proficiency in UVM, SystemVerilog, Verilog, and SVA languages is essential, as well as experience with advanced verification platforms like Palladium Z1, HAPS, or Zebu.

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Excellent communication and teamwork skills are also necessary.

">Seniority Level">

Mid-Senior level

">Employment Type">

Full-time

">Job Function">

Semiconductor Manufacturing