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Engineering Services Specialist

1 week ago

Penang, Malaysia UST Malaysia Full time
Responsibilities and Qualifications

The successful candidate will be responsible for the complete RTL design workflow, from specifications and architecture to the implementation of various IP designs using Verilog. They must have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, and a minimum of 3 years of experience in RTL design with a strong proficiency in Verilog.

  • Develop RTL designs in Verilog for various IP cores, adhering to high design standards and best practices.
  • Collaborate with system architects to understand specifications and requirements for new IP development.
  • Perform functional simulations and static timing analysis to validate designs.
  • Identify and mitigate potential design issues or bottlenecks early in the design process.
  • Support the verification team in developing test plans and test cases specific to the IP being designed.
  • Participate in design reviews, providing constructive feedback and input to improve design quality.
  • Maintain documentation related to design specifications, implementation details, and design flows.
  • Contribute to the continuous improvement of design processes and methodologies.