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Digital Full-Chip Test and Validation Engineer
1 week ago
This Digital Full-Chip Test and Validation Engineer role requires a strong understanding of digital design principles, RTL, and simulation methodologies. Experience with fault simulation and test coverage analysis is also essential.
As a key member of the SOC design and integration team, you will ensure that the DFT infrastructure is correctly implemented. Develop and execute verification plans to validate DFT features such as scan chains, boundary scan (JTAG), built-in self-test (BIST), and memory test infrastructure.
Closely collaborate with design teams to understand the DFT architecture and requirements for various SOC projects. Create and maintain automated testbenches for DFT verification in simulation environments.
Responsibilities:
- Develop and execute verification plans
- Collaborate with design teams to understand DFT architecture and requirements
- Create and maintain automated testbenches for DFT verification
- Perform functional verification of DFT insertion and test features
