UVM and Verilog Language Expert for Verification Tasks
3 days ago
About Us:
UST is a leading provider of verification services and solutions in the semiconductor manufacturing industry.
Key Responsibilities:
- Develop and implement verification methodologies using UVM, SystemVerilog, and Verilog languages
- Collaborate with cross-functional teams to ensure high-quality deliverables
- Contribute to projects requiring advanced verification tools such as Palladium Z1, HAPS, and Zebu platforms
- Possess a strong understanding of firmware development processes and protocols such as SPI, UART, and I2C
Requirements:
- Possesses a Masters or Bachelors degree in Electrical Engineering or Computer Engineering
- At least 3 years of relevant experience in semiconductor manufacturing
- Proficient in UVM, SystemVerilog, Verilog, and SVA languages
- Excellent team player with strong communication skills
- Has experience working with advanced verification platforms like Palladium Z1, HAPS, or Zebu
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