Integration Design Engineer

2 weeks ago

Penang, Malaysia LATTICE SEMICONDUCTOR MALAYSIA SDN. BHD. Full time 60,000 - 120,000 per year

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for.

Responsibilities & Skills

Detailed Description

  • Hardware Integration Design Engineer is responsible for implementation of either sections or full chip, by understanding requirement of individual IPs, how they work together at system level and then SOC them all together.
  • Work includes collaboration with architecture, verification and software teams.
  • Responsibilities include scripting, rtl or schematic design, power and size estimates, generation of the address maps, working with packaging on pin migration, design checks and timing analysis.
  • Experience with timing modeling generation, qualification is an added advantage.

Required Skills, Experience, Licenses:

  • 2yrs experience of hardware integration design
  • Successfully went thru whole development from start to Tape Out.
  • Proficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.
  • Working knowledge of System Verilog, synthesis, and static timing analysis
  • Understanding of DFT methodology on IP and chip level
  • Familiar with floor-planning, power estimate, timing and back-end methodologies
  • Experience with Linux scripting in at least one of shell, and Python
  • Strong written and oral communication skills
  • The ability to stay up-to-date with the latest advancements in technology and design

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