Front End Integration Engineer

1 day ago

Bayan Lepas, Penang, Malaysia UST Malaysia Full time 80,000 - 120,000 per year

We are seeking a Front End Integration Engineer to perform IP level FEInt tasks.

The ideal candidate will have expertise in synthesis, linting, CDC (clock domain crossing), LEC (logical equivalence checking), UPF (Unified Power Format), and other relevant areas.

Responsibilities:

  • Conduct synthesis and optimization of IP blocks
  • Perform linting to ensure code quality and adherence to design guidelines
  • Conduct CDC analysis to identify and address potential issues in clock domains
  • Perform LEC to ensure design consistency before and after synthesis
  • Implement UPF for power management in the design

Qualifications:

  • Wiling to relocate to Penang
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • At least 2 years of experience in front end integration tasks
  • Strong expertise in synthesis, linting, CDC, LEC, and UPF
  • Proficient in industry standard EDA tools
  • Rich verification experience (block or SoC level, simulation, formal verification is an additional advantage)
  • Strong UVM, System Verilog, C++ , Perl, Python knowledge
  • Strong Debug capabilities, master VCS/Verdi/DVE tools
  • Familiar with Standard AMBA/AXI/AHB interface protocol
  • Strong problem-solving, analytical skills, good communication and teamwork skills

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