Formal Verification Engineer

Found in: beBee S MY - 1 month ago

Malaysia Intel Corporation Full time

Formal Verification Engineer page is loaded Formal Verification Engineer Apply locations Malaysia, Penang time type Full time posted on Posted 2 Days Ago job requisition id JR0255567 Job Details: Job Description: 

  • Verification of the microarchitecture using industry standard Formal Verification tools and technologies based on latest model checking and equivalence checking algorithms on world class design IPs (Graphics, Server IPs, processors and SOCs) .
  • Using the hardware architecture design and RTL implementation details, define the Formal Verification scope, deploy the right strategy to prove the correctness while deploying advanced formal techniques, and create abstraction models for convergence on the design, Carve out the right boundaries for the design, create comprehensive Formal Verification test plans, track, verify, apply abstraction techniques and converge on complex designs to deliver a high quality design on schedule and articulate the ROI.
  • Analyses new methodologies, evaluates new tools and corroborate results.
  • May work with vendors on resolving hard design and tool problems.
Qualifications:
  • Bachelors Degree in Engineer (Electrical Engineering, Computer Science or a related field with 3-5 years of experience or (Master's Degree with 1 year of experience in related field
  • As a Datapath Formal Verification Engineer, you will be responsible for ensuring the correctness and reliability of complex digital circuits within the datapath of integrated circuits (ICs).
  • You will utilize formal verification techniques to mathematically prove that the datapath design meets its specified functionality, without relying solely on simulation-based testing.
  • Strong understanding of digital design principles, datapath architecture, and arithmetic units.
  • Proficiency in formal verification methodologies and tools.
  • Experience with hardware description languages (Verilog, VHDL) and formal verification languages (SystemVerilog Assertions, PSL).
  • Familiarity with industry-standard formal verification tools.
  • Excellent problem-solving and debugging skills.
  • Effective communication and teamwork abilities.
  • Must have understanding of digital design principles and good to have Verilog/c++ language
Job Type: Experienced Hire Shift: Shift 1 (Malaysia) Primary Location:  Malaysia, Penang Additional Locations: Business group: In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. About Us

Intel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please click here .

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