Block Level Designer
7 days ago
In this challenging role as a Senior Physical Design Engineer at SignOff Semiconductors, you'll play a critical part in shaping our company's success.
We seek a highly skilled individual with expertise in block/SOC level RTL-gds2 implementation and timing closure.
- A strong background in low power & signoff checks (MVRC/CLP, LEC/Formality, DRC, LVS, IR, EM) is a must.
- Able to write efficient TCL/SHELL/PERL scripts for automation is also necessary.
- Familiarity with Synopsys/Cadence tools is crucial for this position.
Candidates must hold a Bachelor's degree in Electronics & Communication or Electrical & Electronics Engineering, preferably with a Master's in VLSI.
A minimum of 4-7 years of experience is expected.
Role OverviewThis is a mid-senior level position requiring full-time commitment.
Key TasksThe successful candidate will be responsible for implementing low power techniques, executing signoff methodologies, and handling client requirements effectively.
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