Senior Timing Specialist
5 days ago
Job Description
The STA engineer plays a crucial role in overseeing tasks related to timing constraints and closure at block-level and chip-level. Understanding design goals to meet performance/timing requirements, clocking architecture, and relationships is essential.
Key Responsibilities:
- Define timing syntax and signoff requirements.
- Understand clock architecture's impact on timing and performance.
- Closure of CPU/GPU, full chip or large subsystems.
- Experience with Synopsys SDC, Primetime, and STARRC.
- Scripting with TCL, PERL, or Python.
Qualifications:
- Bachelor's or Master's degree in electrical/electronics engineering.
- Minimum 3 years experience analyzing timing in PrimeTime and writing SDC.
- Previous experience in Clock-Tree-Synthesis optimization and clock KPI analysis.
- Prior experience with timing analyzer: Synopsys PrimeTime, Cadence Tempus, Xilinx Vivado, Intel/Altera Quartus.
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