Design Verification

2 days ago


Penang Pulau Pinang Malaysia Uni Connect Full time 80,000 - 120,000 per year

Job Description: Be part of a team in creating state -of -the -art Secure Low Power SoC ARM -based MCU for the  Low -End, Mid -End, and High -end  performance MCU product line in a IC Design Environment Responsibilities: • To develop UVM -based test suite and simulation environment for the verification of standalone IP level and SoC ARM -based system connected with many peripheral digital IPs and Analog IPs. • Capable of designing and building Verification IP from standard industrial specification • To implement test cases from product and standard industrial specification to ensure SoC achieve highest possible coverage, using both constraint -randomized and directed test. • To develop test environment and create test cases with UPF inputs for verification of IPs/SoC level in a multiple power domains SoC to ensure they meet all functional features in their respective power domain. • To document, compile and correlate all test cases to meet all features in Functional Requirement specification • To simulate and debug Gatelevel -Netlist for all corners from back -end team Post layout netlist for all corners to close timing before tape -out. • Capable of debug and working with IP designer to identify failures and also improve on functional and Code coverage. Requirements: • Requires BSc/MSc or PhD in electrical and electronic or Computer engineering • Requires 5 years or more of experience in building UVM/OVM/VMM equivalent test suite • Requires strong understanding of state of the art verification techniques including assertion and metric -driven verification methodology, UVM -based • Very competent  in System Verilog, C++ , C , System C and/or  Verilog • Experience in writing of CPF/UPF to enable multiple power domain verification • Strong experience in working in Synopsys VCS or Cadence IES, and other formal verification tools • Verification experience and working knowledge of ARM based CPU Core , SPI, I2C, UART, I2C,  USB, PCIe , and/or  any other wired protocol with transceivers are strong added advantages • Capable of leading, review  and guiding younger verification engineers in their daily verification tasks • Able to work in a team with a strong drive to excel • Able to work independently on a given assignment and work hard to finish on time • Good written and communication skillsRequirements• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.• 5+ years of experience in SoC/ASIC design verification, with hands -on expertise in UVM and SystemVerilog.• Strong understanding of verification methodologies (UVM/OVM/VMM) and design processes.• Proficiency with simulation tools such as VCS, ModelSim, or Questa.• Experience with scripting languages (Python/Perl/TCL) for automation in verification workflows.• Solid debugging and problem -solving skills.• Excellent communication and teamwork abilities.



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