Package Design Engineer

3 days ago

Penang, Malaysia UST Full time

Key Responsibilities

  • Perform the design and development of multi-layer package substrates (8+ layers) for advanced semiconductor devices.
  • Perform package layout, routing, and stack-up planning using EDA tools (Mentor Graphics, Cadence Allegro, PLA).
  • Ensure designs comply with substrate manufacturing rules (trace width/spacing, via design, impedance requirements).
  • Incorporate assembly rules (die placement, bump/ball pitch, solder joint reliability, warpage control) into package designs.
  • Develop and validate Flip Chip package designs, including bump assignment, redistribution layers (RDL), and underfill considerations.
  • Collaborate with Signal Integrity (SI), Power Integrity (PI), and thermal analysis teams to ensure robust performance.
  • Partner with substrate vendors and OSATs to verify design manufacturability, yield, and assembly feasibility.
  • Provide on-site vendor support when required to resolve design and assembly issues.

Skills & Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Electronics, Materials Science, or related field.
  • 5–8 years of hands-on experience in package design, with proven expertise in multi-layer (8+) substrate design.
  • Proficiency with EDA tools: Mentor Graphics, Cadence Allegro, PLA. (Mentor Graphics Xpedition / Cadence Allegro Package Designer)
  • Strong knowledge of substrate manufacturing rules and assembly rules.
  • Experience with Flip Chip package design methodologies.
  • Familiarity with SI/PI/thermal considerations in advanced packages.
  • Strong communication and collaboration skills for cross-functional and vendor engagement.
  • Flexibility to travel and provide on-site vendor support as needed.

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