Design Verification Engineer

7 days ago

Kuala Lumpur, Kuala Lumpur, Malaysia Zentact Systems Malaysia Full time

Malaysia Hiring

We are seeking an experienced 6 to 10 Years in IP 
Design Verification Engineer
 with expertise in 
SystemVerilog (SV) and UVM methodology
 to verify complex 
IP's and Sub-System
. The ideal candidate will be responsible for developing testbenches, writing test cases, debugging failures, and ensuring high-quality verification closure.

Key Responsibilities:

  • Develop and implement 
    UVM-based testbenches
     for 
    Subsystem, or IP-level verification
    .
  • Create and execute 
    verification plans
    , including test strategies, coverage models, and regression testing.
  • Write 
    System Verilog assertions (SVA), functional coverage, and scoreboards
     to ensure thorough verification.
  • Automate verification flows using 
    Python/Perl/TCL scripts
     for efficiency.
  • Collaborate with cross-functional teams (Design, Validation, Emulation) to ensure high-quality silicon.

Required Skills & Qualifications:

  • 5-15 years
     of hands-on experience in 
    IP/SUB-SYSTEM verification .
  • Strong expertise in 
    SystemVerilog and UVM methodology
    .
  • Deep Understanding of Computer Architecture (X86 or ARM or Any Processor)
  • Experience with IP 
    testbench development from Scratch, constrained random testing, and coverage-driven verification
    .
  • Knowledge of 
    AMBA protocols (AXI, AHB, APB), , or Caches ,Memory Sub-system (Preferred Not Mandatory)
  • Proficiency in scripting languages (
    Python, Perl, TCL, Shell
    ) for automation.
  • Strong debugging and problem-solving skills.
  • Excellent communication and teamwork abilities.

If anyone suits the above requirement please share your resumes to

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