Design Verification Engineer

2 weeks ago


Kuala Lumpur, Kuala Lumpur, Malaysia Tata Consultancy Services (TCS) Full time 80,000 - 120,000 per year

Job Description:

Design Verification expertise in SystemVerilog / C++

  • Experience in test planning and debugging complex designs

  • Full silicon design lifecycle experience

  • Strong background in developing UVM Testbenches from scratch

  • Deep understanding of Computer Architecture

  • Experience with caches and memory subsystems (preferred, but not mandatory)

Location

Kuala Lumpur

Job Function

TECHNOLOGY

Role

Engineer

Job Id

380668

Desired Skills

Design

Desired Candidate Profile

Qualifications : Undergraduate



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