SOC/FPGA Design Verification Engineering Lead/Manager

Job Details
Job Description:
Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation.

As an SME verification engineering lead/manager you will work closely with design teams to architect effective and efficient testbench and verification strategies to promote effective debug and failure detection; build UVM infrastructure including monitors, drivers, and scoreboards; produce functional coverage and code coverage; monitor dashboards and regressions; analyze root cause; develop constrained random stimulus and shape content to effectively stress the design space; and create test plans to ensure functional correctness.

You will lead/manage a team of design verification engineers responsible for IP and SoC design verification. Deploys and manages leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. Works with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture. Collaborates with program leaders on the verification delivery and regression metrics against milestone requirements. Understands security milestone expectations and works with SoC security validation teams to incorporate security-related testing through validation, hackathon reviews, and new validation techniques to improve security coverage. Executes security and security development lifecycle tasks per job role and schedule milestones. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Altera values, developing the capabilities of others, and ensuring a productive work environment.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
• Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests.
• Collaborates and communicates with Architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
• Maintains and improves existing functional verification infrastructure and methodology.
• Absorbs learning from post-silicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products

Qualifications
Minimal Qualification:

• Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 15+ years of technical experience.
• Related technical experience should be in/with: Pre Silicon Validation/Verification, OVM/UVM, System Verilog, constrained random verification methodologies.

Preferred Qualification

• Lead/managed a team of engineers through multiple TO project cycles.
• Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
• The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
• Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.
• Scripting experience with TCL/PERL/Python etc.,
• Formal verification experience
• SME in either Ethernet / PCIe / MACSEC / IPSEC protocols & FPGA architecture or FPGA prototyping

Job Type
Regular

Shift
Shift 1 (Malaysia)

Primary Location:
Penang 15, Penang, Malaysia

Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.