Fip Standard Cell Library Technical Director

1 week ago

Penang, Malaysia INTEL Full time

**Qualifications**:
Required skills/experience: - A high performer with 15+ years of demonstrable experience in most of the standard cell library domains such as circuit design, std cell layouts, extraction, characterization, modeling, physical view abstraction, logic view modeling, reliability and IR drop characterization, validation, quality assurance, documentation and library releases including customer support. - Deep working knowledge of digital logic design and standard cell library development in advanced nodes. - Demonstrated ability to understand and interpret industry benchmarks, create and drive strategies, work independently, and simultaneously manage diverse and extensive assignments while remaining organized and productive in a complex environment. Strong self-initiative, persistence, and ability to deal with a high degree of ambiguity and task and deadline pressure. - Strong written and verbal communication skills. Ability to synthesize abstract complex information into clear messages to create impactful presentations. Preferred skills/experience: - In-depth knowledge in digital design including CMOS combinatorial logic and sequential circuit and layout, and familiarity with design tradeoffs as well as standard cell modeling, extraction, and characterization highly desired. - Familiar with foundry ecosystem and benchmarking practice. Technical, analytical, customer-oriented, and cross-functional collaboration skills. - Ability to work in a dynamic and matrix team-oriented environment. - Experience in designing flips flops, clock gating cells, level shifters, power gating cells and other complex circuits. - Clear understanding of CMOS device characteristics and design rules in submicron process nodes. Knowledge of submicron process issues, especially in FINFET technologies. Familiarity in high sigma variation analysis in smaller technology nodes. - Experience in standard cell circuits optimization to achieve better PPA. Familiarity with layout design and experience in working with layout designers to optimize layout parasitic to achieve target PPA. - Involvement in layout extraction and understanding of layout dependent parameters in the extracted netlist. - Understanding of timing/leakage characterization of Standard cells. - Scripting capability in TCL/PERL/Python. Strong Analytical and Logical skills. #DesignEnablement

**Inside this Business Group**:
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art - from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

**Posting Statement**:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Benefits**:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

**Working Model**:
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. **In certain circumstances the work model may change to accommodate business needs.**

**Position of Trust**
JobType

Hybrid

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